1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a synchronous semiconductor memory device having a prefetch operation mode, which is capable of minimizing the number of main data lines.
2. Discussion of Related Art
Electronic systems, such as computers, are being used in almost every aspect of business and home life. These computers are becoming faster and are increasing in their storage capacity. Memory devices for these systems also need to increase in speed and in storage capacity. To realize an increase in both speed and memory storage capacity, semiconductor memory devices used in these electronic systems need to have a higher degree of integration and increased data transmission rates. To increase the rate of data transmission, both a double data rate (DDR) system and a pipelined burst system have been disclosed in the prior art. In each of these prior art systems, a prefetch operation reads the data internally from a memory cell before the data is to be output externally.
In a semiconductor memory operating at a double data rate (FIG. 5 shows signals used to drive DDR systems), two or more data segments are successively output from a single input/output (I/O) port during a single read period. To do this, the data segments must be prefetched because it is difficult to perform two read operations during one period. In other words, two or more data segments must be read from the memory cell and latched to an interior latch before being externally outputted. The data must also be able to be outputted right away through the I/O port when a clock for a data output is provided. In a single data rate (SDR) system (FIG. 6 shows signals used to drive SDR systems), by contrast, only one data is output per I/O port per read period.
FIG. 1 depicts a block diagram of a read section of a semiconductor memory device according to the prior art. Several problems with the prefetch operation in the conventional systems will become apparent from the following description of the prior art made with reference to FIG. 1. As shown in FIG. 1, a conventional read section of a memory device includes a memory cell array divided into block units. Each memory cell array block 10-10n corresponds to one of the block sense amplifier arrays 20-20n. An output line from each block sense amplifier array 20-20n is connected to a corresponding one of a plurality of main data lines L1-Ln. Each of the main data lines L1-Ln is, in turn, connected to a corresponding one of the data output buffers 30-30n. 
A data read operation in the device constructed as shown in FIG. 1 is as follows. Data read from memory cells within a selected one of the memory cell array blocks 10-10n is amplified through a corresponding one of the block sense amplifiers 20-20n. For example, if a first sense amplifier of the block sense amplifier array 20 operates, then the data amplified in the block sense amplifier array 20 enters the data output buffer 30 through the main data line L1. To provide a double data rate, the data must enter the data output buffer before a clock for data output is provided.
Unfortunately, in a semiconductor device having the structure of FIG. 1, the prefetched data cannot be transmitted to the data output buffer through the main data line L1 which is already being used. Another main data line is therefore required to transfer the prefetched data. Because of this, to enable a prefetch operation, the number of main data lines in the prior art systems needs to be multiplied by the number of data segments that are to be outputted per I/O port per read cycle.
Also unfortunately, an increase in the number of main data lines increases the area occupied by the read circuit within a chip and hence the overall size of the chip. This increase in chip size also increases the cost of producing the chips and hence the corresponding price for the products incorporating those chips. Furthermore, because a charge or discharge operation must be performed to drive the main data lines to their high or low levels, the peak electric current increases with an increase in the number of main data lines resulting in an increase in the electric power consumption by the chip.
Accordingly, the industry requires a technique for increasing the data rate of a semiconductor memory device without increasing chip size or power consumption. A prefetch system and method that does not require an increase in the number of main data lines would be ideal.
According to the needs of the industry, the present invention enables a semiconductor memory device that substantially overcomes several disadvantages of the prior art.
A primary object of the present invention is to provide a semiconductor device capable of increasing a data read rate of the semiconductor memory device without substantially increasing the size or power consumption of the device.
Another object of the present invention is to provide a semiconductor memory device that includes a prefetch operation mode and a data transmitting method with a reduced number of main data lines as compared to the prior art.
A further object of the present invention is to provide a semiconductor memory device and a data transmitting method therefor, which includes a prefetch operation mode capable of optimizing the number of main data lines.
A still further object of the invention is to provide a double data rate type semiconductor memory device and a data transmitting method therefor, in which a chip size and a consumption of peak electric current are minimized.
An additional object of the invention is to provide a static random access memory (SRAM) device capable of performing a prefetch operation without increasing the number of data lines.
To achieve these and other advantages, a semiconductor memory device having a prefetch operation mode and a data transfer method for reducing the number of main data lines is provided. Similar to the prior art, the semiconductor memory device according to a first preferred embodiment of this invention has a plurality of main data lines connected between the block sense amplifier arrays and the data output buffers. The block sense amplifiers prefetch cell data from numerous memory cells and transmit the data to the main data lines. Each main data line corresponds to one input/output port.
Unlike the prior art, however, a pass/latch part is arranged in communication with a back (downstream) portion of the block sense amplifier, and is connected between the block sense amplifier and a corresponding main data line. The pass/latch part receives multiple cell data segments in parallel from the block sense amplifiers and transmits them in series to the corresponding main data line. In this manner, a plurality of cell data segments are separated through the pass/latch part, and are transmitted to the same main data line. In other words, according to this invention, a plurality of cell data segments can be prefetched and transmitted through a single main data line, to thereby reduce the number of main data lines required to perform a prefetch operation.